In a typical output boost regulator, the output voltage is controlled by an electronic circuit that measures a level of the output voltage, compares that measured level to a predetermined desired level, and develops a response to that comparison elsewhere in the circuit in order to more accurately achieve the desired output voltage.
Even though the prior art in FIG. 1 teaches an output boost regulator for a single load RL, the prior art does not address the needs of a multiple load output boost regulator wherein the voltage level (Vout) for each load can be different. FIG. 1 illustrates a prior art switching mode output boost regulator that uses a trailing edge modulation control scheme. The input voltage VIN is coupled to a first terminal of an inductor L1. A second terminal of the inductor L1 is coupled to a first terminal of a switch SW1 and to an anode of a diode D1. A capacitor C1 is coupled between a cathode of the diode D1 and a second terminal of the switch SW1. A load RL is coupled across the capacitor C1. A potentiometer PT1 is coupled across the load RL and provides a negative input to an error amplifier 10. A reference voltage REF is coupled to a positive input to the error amplifier 10. An output VEAO of the error amplifier 10 is coupled to a positive input to a pulse width modulating comparator 14. A negative input to the comparator 14 is coupled to receive a ramp output of an oscillator 12. An output of the comparator 14 is coupled as an inverted reset input R of a flip-flop 16. An input D of the flip-flop 16 is coupled to an inverted output Q of the flip-flop 16. A clock input CLK of the flip-flop 16 is coupled to a clock output of the oscillator 12. An output Q of the flip-flop 16 is coupled to control the state of the switch SW1.
The output voltage VOUT supplied to the load RL is formed by integrating the inductor current I1 in the capacitor C1. Pulse width modulation (PWM) is used to modulate the width of voltage pulses that control the switch SW1, maintaining the output voltage VOUT at a constant level. Energy from the input source VIN is stored in the inductor L1 when the switch SW1 is closed. When the switch SW1 is open, energy from the inductor L1 is transferred to the capacitor C1 and to the load RL. A predetermined fraction of the output voltage VOUT is formed by the potentiometer PT1. This voltage VFB is input into the negative terminal of the error amplifier 10 for comparison to the reference voltage REF. The comparison determines how close the actual output voltage VOUT is to the desired output voltage and is used to modulate the width of the pulses that control the switch SW1.
FIG. 1 illustrates a trailing edge pulse width modulation scheme for controlling the switch SW1. In trailing edge modulation, the switch SW1 turns on (closes) on the trailing edge of the clock signal. The leading edge of the clock signal may also be utilized to implement leading edge modulation. For a leading edge modulation control scheme, the inputs to the error amplifier 10 are reversed: the voltage VFB from the potentiometer PT1 is coupled to the positive terminal of the voltage error amplifier 10 and the reference voltage REF is coupled to the negative terminal of the voltage error amplifier 10. Further, for a leading edge modulation control scheme, the control voltage VSW1 is also reversed. The control voltage VSW1 is taken directly from the output Q of the flip-flop 16 instead of from the output Q.
FIGS. 2, 3 and 4 show voltage waveforms with respect to time of various voltage levels within the switch control circuitry 31 illustrated in FIG. 1. The time axis in each of FIGS. 2, 3 and 4 has been drawn to correspond to the others. FIG. 2 illustrates the voltage levels with respect to time of the error amplifier output VEAO and the modulating ramp output of the oscillator 12. FIG. 3 illustrates the voltage level with respect to time of the control voltage VSW1 for the switch SW1. The switch SW1 is "on" or closed when the control voltage VSW1 is at a high voltage level. The switch SW1 is "off" or open when the control voltage is at a low voltage level. FIG. 4 illustrates the clock impulses with respect to time of the clock output of the oscillator 12.
The switch SW1 turns on after the trailing edge of the system clock. Once the switch SW1 is on, the inductor current IL will ramp up and the modulating comparator 14 then compares the error amplifier output voltage VEAO and the modulating ramp RAMP. When the signal RAMP is higher than the signal VEAO, the output of the comparator 14 will fall to a logical low voltage level. Due to the inverter at its input, the input R of the flip-flop 16 will then rise to a logical high voltage level thereby resetting the output Q of the flip-flop 16 to a logical low voltage level and turning off the switch SW1. The duty cycle is determined as a ratio of the on time of the switch to its off time.
Prior art FIG. 5 illustrates a multiple output flyback regulator that allows a different output voltage at each load . However, it will be shown that changing the desired output voltage at any of the loads requires modifying the number of windings in the corresponding inductor associated with that particular load. Further, once such a circuit is constructed, modifying the number of windings would be impractical. A voltage source VIN is coupled to a first terminal of a primary transformer winding L10 and coupled to supply power to an integrated circuit chip controller 100. The first terminal of the transformer winding L10 is designated with a "dot" to show polarity of the primary transformer winding L10 with reference to secondary transformer windings to be discussed below. According to the "dot convention," current entering the primary transformer winding terminal designated with a dot will continue to flow into the dot in the secondary windings when Q10 is open.
A second terminal of the primary transformer winding L10 is coupled to a drain of an NMOSFET Q10. A source of the transistor Q10 is coupled to a ground node. A gate of the transistor Q10 is coupled to be controlled by the controller 100 by a signal designated OUT1. A gate of an NMOSFET Q11, a gate of an NMOSFET Q12 and a gate of an NMOSFET Q13 are all coupled to be controlled by the controller 100 by a signal designated OUT2. A drain of the transistor Q11 is coupled to a first terminal of a secondary transformer winding L11. The secondary transformer winding L11 is inductively coupled to the primary transformer winding L10. The first terminal of the secondary transformer winding L11 is designated with a dot with reference to the primary transformer winding L10. A second terminal of the secondary transformer winding L11 is coupled to a first terminal of a capacitor C11, a first terminal of a load resistor RL2, and an output voltage node VOUT2. A second terminal of the capacitor C11 and a second terminal of the load resistor RL2 are coupled to the ground node.
A drain of the transistor Q12 is coupled to a first terminal of a secondary transformer winding L12. The secondary transformer winding L12 is inductively coupled to the primary transformer winding L10. The first terminal of the secondary transformer winding L12 is designated with a dot with reference to the primary transformer winding L10. A second terminal of the transformer winding L12 is coupled to a first terminal of a capacitor C12, a first terminal of a load resistor RL1, an output voltage node VOUT1, and the controller 100 for providing a feedback voltage signal VFB to the controller 100 (VOUT1 is equivalent to VFB). A second terminal of the capacitor C12 and a second terminal of the load resistor RL1 are coupled to the ground node.
A drain of the transistor Q13 is coupled to a first terminal of a secondary transformer winding L13. The secondary transformer winding L13 is inductively coupled to the primary transformer winding L10. The first terminal of the secondary transformer winding L13 is designated with a dot with reference to the primary transformer winding L10. A second terminal of the secondary transformer winding L13 is coupled to a first terminal of a capacitor C13, a first terminal of a load resistor RL3, and an output voltage node VOUT3. A second terminal of the capacitor C13 and a second terminal of the load resistor RL3 are coupled to the ground node.
A source of the transistor Q11 is coupled to a first terminal of a resistor R11 and to the controller 100 for providing a current sensing voltage signal SENSE to the controller 100. A source of the transistor Q12 is coupled to a second terminal of the resistor R11 and to a first terminal of a resistor R12. A source of the transistor Q13 is coupled to a second terminal of the resistor R12 and to a first terminal of a resistor R13. A second terminal of the resistor R13 is coupled to the ground node.
In the prior art in FIG. 5, the output voltages (VOUT1, VOUT2, and VOUT3) are dependent on the ratio between the primary and secondary transformer ratio windings. If a particular output voltage for a load needed to be modified, the number of windings in the second transformer attached to that load would need to be changed in order to achieve the desired output voltage. Physically changing the secondary transformer in the circuit would be impractical.
What is needed is a multiple output boost regulator having the ability to provide two or more output voltages from one input voltage and one inductor and that can easily change the predetermined output voltage for each load.